The present invention relates generally to semiconductor fabrication and more specifically to semiconductor plating/chemical mechanical polishing (CMP) processes.
RF MOS devices generally utilize the standard lateral MOS device with a diffused via that connects the source and the body to the back side of the chip such that the backside becomes both the electrical and thermal ground. Some lateral RF MOS devices utilize non-diffusion source-backside connection.
For example, U.S. Pat. No. 6,048,772 to D""Anna describes a method of fabricating a lateral RF MOS device with a non-diffusion source-backside connection between source and drain.
U.S. Pat. No. 5,900,663 to Johnson et al. describes a quasi-mesh gate structure for lateral RF MOS transistor having a conductive plug source-body-backside connection.
U.S. Pat. Nos. 6,063,678 to D""Anna and 5,949,104 to D""Anna each describe lateral RF devices.
Accordingly, it is an object of the present invention to provide a self-aligned metal plating/CMP process for RF lateral MOS devices.
Another object of the present invention is to provide a self-aligned copper plating/CMP process for RF lateral MOS devices.
A further object of the present invention is to provide a lower cost and simple fabrication self-aligned copper plating/CMP process for RF lateral MOS devices.
Yet another object of the present invention is to provide a self-aligned copper plating/CMP process for RF lateral MOS devices that provides an automatic metal separation between poly, S/D and others by sidewall spacer.
Another object of the present invention is to provide a self-aligned copper plating/CMP process that provides high current density RF lateral MOS devices while shrinking the devices to enhance performance.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate having a gate oxide layer formed thereover is provided. A first layer of polysilicon is formed over the gate oxide layer. A second layer of material is formed over the polysilicon layer. The polysilicon and the second layer of material are patterned to form a gate having exposed sidewalls with the gate having a lower patterned polysilicon layer and an upper patterned second material layer. Sidewall spacers are formed on the exposed sidewalls of the gate. The upper patterned second material layer of the gate is removed to form a cavity above the patterned polysilicon layer and between the sidewall spacers. A planarized copper plug is formed within the cavity.